MT40A1G8WE-083E Datasheet, PDF (129/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Hard Post Package Repair
nor HIGH for equal to or longer than 2^tCK, then hPPR mode execution
is unknown.
c. DQS should function normally.
4. REF commands may NOT be issued at anytime while in PPT mode.
5. Issue PRE after ^tPGM time so that the device can repair the target row during
t_{PGM time.}
a. Wait ^tPGM_Exit after PRE to allow the device to recognize the repaired target
row address.
6. Issue MR4[13] 0 command to hPPR mode disable.
a. Wait ^tPGMPST for hPPR mode exit to complete.
b. After ^tPGMPST has expired, any valid command may be issued.
The entire sequence from hPPR mode enable through hPPR mode disable may be re-
peated if more than one repair is to be done.
After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if
the device is to be accessed.
After hPPR mode has been exited, the DRAM controller can confirm if the target row
was repaired correctly by writing data into the target row and reading it back.
Figure 71: hPPR WR – Entry
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CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
129
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