MT40A1G8WE-083E Datasheet, PDF (181/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Bank Access Operation
Table 69: DDR4 Bank Group Timing Examples (Continued)
Parameter
t_{WTR_L}
DDR4-1600
4nCK or 7.5ns
DDR4-2133
4nCK or 7.5ns
DDR4-2400
4nCK or 7.5ns
Notes:
1. Refer to Timing Tables for actual specification values, these values are shown for refer-
ence only and are not verified for accuracy.
2. Timings with both nCK and ns require both to be satisfied; that is, the larger time of the
two cases must be satisfied.
Figure 113: READ Burst ^tCCD_S and ^tCCD_L Examples
CK_c
T0
T1
T2
T3
T4
T5
T6
CK_t
Command _READ
DES
DES
DES
READ
DES
DES
t_{CCD_S}
Bank Group
(BG)
BG a
BG b
Bank Bank c
Bank c
T7
T8
DES
DES
t_{CCD_L}
T9
T10
T11
DES
READ
DES
BG b
Bank c
Address Col n
Col n
Col n
Don’t Care
Notes:
1. ^tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank
groups (T0 to T4).
2. ^tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank
group (T4 to T10).
Figure 114: Write Burst ^tCCD_S and ^tCCD_L Examples
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
Command WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
WRITE
DES
t_{CCD_S}
t_{CCD_L}
Bank Group
(BG)
BG a
BG b
BG b
Bank Bank c
Bank c
Bank c
Address
Coln
Coln
Coln
Don’t Care
Notes:
1. ^tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank
groups (T0 to T4).
2. ^tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank
group (T4 to T10).
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
181
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