MT40A1G8WE-083E Datasheet, PDF (157/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
ODT Input Buffer Disable Mode for Power-Down
ODT Input Buffer Disable Mode for Power-Down
ODT input buffer disable mode, when enabled via MR5[5], will prevent the device from
providing R_TT(NOM) termination during power-down for additional power savings.
The internal delay on the CKE path to disable the ODT buffer and block the sampled
output must be accounted for; therefore, ODT must be continuously driven to a valid
level, either LOW or HIGH, when entering power-down. However, after ^tCPDED (MIN)
has been satisfied, the ODT signal may float.
When ODT input buffer disable mode is enabled, R_TT(NOM) termination corresponding
to sampled ODT after CKE is first registered LOW (and ^tANPD before that) may not be
provided. ^tANPD is equal to (WL - 1) and is counted backward from PDE, with CKE reg-
istered LOW.
Figure 99: ODT Power-Down Entry with ODT Buffer Disable Mode
diff_CK
CKE
ODT
DRAM_R_{TT_sync}
(DLL enabled)
CA parity disabled
DRAM_R_{TT_sync}
(DLL enabled)
CA parity enabled
t_{DODTLoff +1}
t_{CPDED (MIN)}
R_TT(NOM)
DODTLoff
R_TT(NOM)
DODTLoff
Floating
t_{ADC (MIN)}
R_TT(Park)
t_{CPDED (MIN) +} t_{ADC (MAX)}
t_{ADC (MIN)}
R_TT(Park)
t_{CPDED (MIN) +} t_{ADC (MAX) + PL}
DRAM_R_{TT_async}
(DLL disabled)
R_TT(NOM)
t_{AONAS (MIN)}
t_{CPDED (MIN) +} t_{AOFAS (MAX)}
R_TT(Park)
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
157
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