MT40A1G8WE-083E Datasheet, PDF (71/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Write Leveling
and ^tDSH specifications also need to be fulfilled. One way to achieve this is to combine
the actual ^tDQSS in the application with an appropriate duty cycle and jitter on the DQS
signals. Depending on the actual ^tDQSS in the application, the actual values for ^tDQSL
and ^tDQSH may have to be better than the absolute limits provided in the AC Timing
Parameters section in order to satisfy ^tDSS and ^tDSH specifications. A conceptual tim-
ing of this scheme is shown below.
Figure 16: Write Leveling Concept, Example 1
T0
T1
T2
T3
T4
T5
T6
T7
Source
CK_c
CK_t
diff_DQS
Tn
T0
T1
T2
T3
T4
T5
T6
Destination ^CK_c
CK_t
diff_DQS
DQ
0 or 1
0
0
0
diff_DQS
Push DQS to capture
the 0-1 transition
DQ
0 or 1
1
1
1
DQS driven by the controller during leveling mode must be terminated by the DRAM
based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be
terminated at the controller.
All data bits carry the leveling feedback to the controller across the DRAM configura-
tions: x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently.
Therefore, a separate feedback mechanism should be available for each byte lane. The
upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-to-
clock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)-
to-clock relationship.
The figure below is another representative way to view the write leveling procedure. Al-
though it shows the clock varying to a static strobe, this is for illustrative purpose only;
the clock does not actually change phase, the strobe is what actually varies. By issuing
multiple WL bursts, the DQS strobe can be varied to capture with fair accuracy the time
at which the clock edge arrives at the DRAM clock input buffer.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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