MT40A1G8WE-083E Datasheet, PDF (59/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 5
Data Mask
The DATA MASK (DM) function, also described as a partial write, has been added to the
device and is supported only for x8 and x16 configurations (x4 is not supported). The
DM function shares a common pin with the DBI and TDQS functions. The DM function
applies only to WRITE operations and cannot be enabled at the same time the write DBI
function is enabled. Refer to the TDQS Function Matrix table for valid configurations for
all three functions (TDQS/DM/DBI).
CA Parity Persistent Error Mode
Normal CA parity mode (CA parity persistent mode disabled) no longer performs CA
parity checking while the parity error status bit remains set at 1. However, with CA pari-
ty persistent mode enabled, CA parity checking continues to be performed when the
parity error status bit is set to a 1.
ODT Input Buffer for Power-Down
This feature determines whether the ODT input buffer is on or off during power-down.
If the input buffer is configured to be on (enabled during power-down), the ODT input
signal must be at a valid logic level. If the input buffer is configured to be off (disabled
during power-down), the ODT input signal may be floating and the device does not pro-
vide R_TT(NOM) termination. However, the device may provide R_TT(Park) termination de-
pending on the MR settings. This is primarily for additional power savings.
CA Parity Error Status
The device will set the error status bit to 1 upon detecting a parity error. The parity error
status bit remains set at 1 until the device controller clears it explicitly using an MRS
command.
CRC Error Status
The device will set the error status bit to 1 upon detecting a CRC error. The CRC error
status bit remains set at 1 until the device controller clears it explicitly using an MRS
command.
CA Parity Latency Mode
CA parity is enabled when a latency value, dependent on ^tCK, is programmed; this ac-
counts for parity calculation delay internal to the device. The normal state of CA parity
is to be disabled. If CA parity is enabled, the device must ensure there are no parity er-
rors before executing the command. CA parity signal (PAR) covers ACT_n, RAS_n/A16 ,
CAS_n/A15, WE_n/A14, and the address bus including bank address and bank group
bits. The control signals CKE, ODT, and CS_n are not included in the parity calculation.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
59
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.