MT40A1G8WE-083E Datasheet, PDF (347/358 Pages) Micron Technology – Automotive DDR4 SDRAM

Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
Parameter
Data setup time to
Base (calibrated
DQS_t, DQS_c
V_REF)
Non-calibrated
V_REF
Data hold time from Base (calibrated
DQS_t, DQS_c
V_REF)
Non-calibrated
V_REF
DQ and DM minimum data pulse width
for each input
DQS_t, DQS_c to DQ skew, per group, per
access
DQ output hold time from DQS_t, DQS_c
Data Valid Window per device: ^tQH -
t_{DQSQ each device’s output per IU}
Data Valid Window per device, per pin:
t_{QH -} t_{DQSQ each device’s output per IU}
DQ Low-Z time from CK_t, CK_c
DQ High-Z time from CK_t, CK_c
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 1^tCKpreamble
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 2^tCKpreamble
DQS_t, DQS_c differential input low pulse
width
DQS_t, DQS_c differential input high
pulse width
DQS_t, DQS_c falling edge setup to CK_t,
CK_c rising edge
Symbol
t_DS
t_{PDA_S}
DDR4-2666
DDR4-2933
DDR4-3200
Reserved
Min Max Min Max Min Max Min Max
DQ Input Timing
Refer to DQ Input Receiver Specification section
(approximately 0.15^tCK to 0.28^tCK )
minimum of 0.5ui
t_DH
t_{PDA_H}
Refer to DQ Input Receiver Specification section
(approximately 0.15^tCK to 0.28^tCK )
minimum of 0.5UI
t_DIPW
0.58
–
0.58
–
0.58
–
DQ Output Timing (DLL enabled)
t_DQSQ
–
0.18
–
0.19
–
0.22
t_QH
t_DVWd
t_DVWp
t_LZDQ
t_HZDQ
t_DQSS1ck
t_DQSS2ck
t_DQSL
0.74
–
0.74
–
0.74
–
0.64
–
0.64
–
0.64
–
0.72
–
0.72
–
0.72
–
–310 170 –280 165 –250 160
–
170
–
165
–
160
DQ Strobe Input Timing
–0.27 0.27 –0.27 0.27 –0.27 0.27
–0.50 0.50 –0.50 0.50 –0.50 0.50
0.46 0.54 0.46 0.54 0.46 0.54
t_DQSH
0.46 0.54 0.46 0.54 0.46 0.54
t_DSS
0.18
–
0.18
–
0.18
–
Unit
–
UI
–
UI
UI
UI
UI
UI
UI
ps
ps
CK
CK
CK
CK
CK
Notes