MT40A1G8WE-083E Datasheet, PDF (102/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Command/Address Parity
occurs during the ^tPAR_UNKNOWN window, the WRITE CRC Error Status Bit lo-
cated at MR5[3] may or may not get set. When CA Parity and WRITE CRC are both
enabled and a CA Parity occurs, the WRITE CRC Error Status Bit should be reset.
2. Log the error by storing the erroneous command and address bits in the MPR er-
ror log.
3. Set the parity error status bit in the mode register to 1. The parity error status bit
must be set before the ALERT_n signal is released by the DRAM (that is,
t_{PAR_ALERT_ON +} t_{PAR_ALERT_PW (MIN)).}
4. Assert the ALERT_n signal to the host (ALERT_n is active LOW) within
t_{PAR_ALERT_ON time.}
5. Wait for all in-progress commands to complete. These commands were received
t_{PAR_UNKOWN before the erroneous command.}
6. Wait for ^tRAS (MIN) before closing all the open pages. The DRAM is not executing
any commands during the window defined by (^tPAR_ALERT_ON +
t_{PAR_ALERT_PW ).}
7. After ^tPAR_ALERT_PW (MIN) has been satisfied, the device may de-assert
ALERT_n.
a. When the device is returned to a known precharged state, ALERT_n is al-
lowed to be de-asserted.
8. After (^tPAR_ALERT_PW (MAX)) the DRAM is ready to accept commands for nor-
mal operation. Parity latency will be in effect; however, parity checking will not re-
sume until the memory controller has cleared the parity error status bit by writing
a zero. The DRAM will execute any erroneous commands until the bit is cleared;
unless persistent mode is enabled.
• The DRAM should have only DES commands issued around ALERT_n going HIGH
such that at least 3 clocks prior and 1 clock plus 3ns after the release of ALERT_n.
• It is possible that the device might have ignored a REFRESH command during
t_{PAR_ALERT_PW or the REFRESH command is the first erroneous frame, so it is rec-}
ommended that extra REFRESH cycles be issued, as needed.
• The parity error status bit may be read anytime after ^tPAR_ALERT_ON +
t_{PAR_ALERT_PW to determine which DRAM had the error. The device maintains the}
error log for the first erroneous command until the parity error status bit is reset to a
zero or a second CA parity occurs prior to resetting.
The mode register for the CA parity error is defined as follows: CA parity latency bits are
write only, the parity error status bit is read/write, and error logs are read-only bits. The
DRAM controller can only program the parity error status bit to zero. If the DRAM con-
troller illegally attempts to write a 1 to the parity error status bit, the DRAM can not be
certain that parity will be checked; the DRAM may opt to block the DRAM controller
from writing a 1 to the parity error status bit.
The device supports persistent parity error mode. This mode is enabled by setting
MR5[9] = 1; when enabled, CA parity resumes checking after the ALERT_n is de-asser-
ted, even if the parity error status bit remains a 1. If multiple errors occur before the er-
ror status bit is cleared the error log in MPR Page 1 should be treated as "Don’t Care." In
persistent parity error mode the ALERT_n pulse will be asserted and de-asserted by the
DRAM as defined with the MIN and MAX value ^tPAR_ALERT_PW. The DRAM controller
must issue DESELECT commands once it detects the ALERT_n signal, this response
time is defined as ^tPAR_ALERT_RSP. The following figures capture the flow of events on
the CA bus and the ALERT_n signal.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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