MT40A1G8WE-083E Datasheet, PDF (15/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Table 51: ^tREFI and ^tRFC Parameters ............................................................................................................. 140
Table 52: Power-Down Entry Definitions ....................................................................................................... 149
Table 53: CRC Error Detection Coverage ........................................................................................................ 160
Table 54: CRC Data Mapping for x4 Devices, BL8 ........................................................................................... 162
Table 55: CRC Data Mapping for x8 Devices, BL8 ........................................................................................... 162
Table 56: CRC Data Mapping for x16 Devices, BL8 ......................................................................................... 163
Table 57: CRC Data Mapping for x4 Devices, BC4 ........................................................................................... 163
Table 58: CRC Data Mapping for x8 Devices, BC4 ........................................................................................... 164
Table 59: CRC Data Mapping for x16 Devices, BC4 ......................................................................................... 165
Table 60: DBI vs. DM vs. TDQS Function Matrix ............................................................................................. 170
Table 61: DBI Write, DQ Frame Format (x8) ................................................................................................... 170
Table 62: DBI Write, DQ Frame Format (x16) ................................................................................................. 170
Table 63: DBI Read, DQ Frame Format (x8) .................................................................................................... 171
Table 64: DBI Read, DQ Frame Format (x16) .................................................................................................. 171
Table 65: DM vs. TDQS vs. DBI Function Matrix ............................................................................................. 172
Table 66: Data Mask, DQ Frame Format (x8) .................................................................................................. 172
Table 67: Data Mask, DQ Frame Format (x16) ................................................................................................ 172
Table 68: CWL Selection ............................................................................................................................... 175
Table 69: DDR4 Bank Group Timing Examples .............................................................................................. 180
Table 70: Read-to-Write and Write-to-Read Command Intervals .................................................................... 185
Table 71: Termination State Table ................................................................................................................. 247
Table 72: Read Termination Disable Window ................................................................................................. 247
Table 73: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 .......................................................... 248
Table 74: Dynamic ODT Latencies and Timing (1^tCK Preamble Mode and CRC Disabled) ................................ 251
Table 75: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix ............................ 252
Table 76: Absolute Maximum Ratings ............................................................................................................ 255
Table 77: Temperature Range ........................................................................................................................ 255
Table 78: Recommended Supply Operating Conditions .................................................................................. 256
Table 79: V_DD Slew Rate ................................................................................................................................ 256
Table 80: Leakages ....................................................................................................................................... 257
Table 81: V_REFDQ Specification ...................................................................................................................... 258
Table 82: V_REFDQ Range and Levels ................................................................................................................ 259
Table 83: RESET_n Input Levels (CMOS) ....................................................................................................... 260
Table 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 ........................................... 260
Table 85: Command and Address Input Levels: DDR4-2666 ............................................................................ 261
Table 86: Command and Address Input Levels: DDR4-2933 and DDR4-3200 ................................................... 261
Table 87: Single-Ended Input Slew Rates ....................................................................................................... 262
Table 88: Command and Address Setup and Hold Values Referenced – AC/DC-Based ..................................... 263
Table 89: Derating Values for ^tIS/^tIH – AC100DC75-Based .............................................................................. 263
Table 90: Derating Values for ^tIS/^tIH – AC90/DC65-Based .............................................................................. 264
Table 91: DQ Input Receiver Specifications .................................................................................................... 265
Table 92: Rx Mask and ^tDS/^tDH without Write Training .................................................................................. 268
Table 93: TEN Input Levels (CMOS) .............................................................................................................. 268
Table 94: CT Type-A Input Levels .................................................................................................................. 269
Table 95: CT Type-B Input Levels .................................................................................................................. 270
Table 96: CT Type-C Input Levels (CMOS) ..................................................................................................... 270
Table 97: CT Type-D Input Levels .................................................................................................................. 271
Table 98: Differential Input Swing Requirements for CK_t, CK_c ..................................................................... 273
Table 99: Minimum Time AC Time ^tDVAC for CK ........................................................................................... 273
Table 100: Single-Ended Requirements for CK ............................................................................................... 274
Table 101: CK Differential Input Slew Rate Definition ..................................................................................... 274
Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400 ................ 276
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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