PIC16F882_09 Datasheet, PDF (95/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/S-0
R/S-0
U-0
R/W-0
SR1⁽²⁾
SR0⁽²⁾
C1SEN
C2REN
PULSS
PULSR
—
FVREN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
S = Bit is set only -
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SR1: SR Latch Configuration bit⁽²⁾
1 = C2OUT pin is the latch Q output
0 = C2OUT pin is the C2 comparator output
bit 6
SR0: SR Latch Configuration bits⁽²⁾
1 = C1OUT pin is the latch Q output
0 = C1OUT pin is the C1 Comparator output
bit 5
C1SEN: C1 Set Enable bit
1 = C1 comparator output sets SR latch
0 = C1 comparator output has no effect on SR latch
bit 4
C2REN: C2 Reset Enable bit
1 = C2 comparator output resets SR latch
0 = C2 comparator output has no effect on SR latch
bit 3
PULSS: Pulse the SET Input of the SR Latch bit
1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 2
PULSR: Pulse the Reset Input of the SR Latch bit
1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 1
Unimplemented: Read as ‘0’
bit 0
FVREN: Fixed Voltage Reference Enable bit
1 = 0.6V Reference FROM INTOSC LDO is enabled
0 = 0.6V Reference FROM INTOSC LDO is disabled
Note 1:
2:
The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on
the pin), regardless of the SR latch operation.
To enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly
configured.
© 2009 Microchip Technology Inc.
DS41291F-page 93