PIC16F882_09 Datasheet, PDF (203/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
13.4.10 ACKNOWLEDGE SEQUENCE TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN (SSPCON2
register). When this bit is set, the SCL pin is pulled low
and the contents of the Acknowledge Data bit (ACKDT)
is presented on the SDA pin. If the user wishes to gener-
ate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG) and
the SCL pin is de-asserted (pulled high). When the SCL
pin is sampled high (clock arbitration), the Baud Rate
Generator counts for TBRG. The SCL pin is then pulled
low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 13-17).
13.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
13.4.11 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2 register). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high, and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be de-asserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT regis-
ter) is set. A TBRG later, the PEN bit is cleared and the
SSPIF bit is set (Figure 13-18).
13.4.11.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 13-17: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
SDA
D0
TBRG
TBRG
ACK
ACKEN automatically cleared
SCL
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Note: TBRG = one Baud Rate Generator period.
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
© 2009 Microchip Technology Inc.
DS41291F-page 201