PIC16F882_09 Datasheet, PDF (273/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
TABLE 17-16: I²C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min. Max. Units
Conditions
100*
101*
102*
103*
90*
91*
106*
107*
92*
109*
110*
*
Note 1:
2:
THIGH Clock high time
100 kHz mode
4.0
—
μs Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
μs Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY —
TLOW Clock low time
100 kHz mode
4.7
—
μs Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
μs Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY —
TR
SDA and SCL rise 100 kHz mode
—
1000 ns
time
400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
TF
SDA and SCL fall 100 kHz mode
—
300 ns
time
400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
TSU:STA Start condition
100 kHz mode
4.7
—
μs Only relevant for
setup time
400 kHz mode
0.6
—
μs ^{Repeated Start condition}
THD:STA Start condition hold 100 kHz mode
4.0
—
μs After this period the first
time
400 kHz mode
0.6
—
μs ^{clock pulse is generated}
THD:DAT Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9 μs
TSU:DAT Data input setup 100 kHz mode
250
—
ns (Note 2)
time
400 kHz mode
100
—
ns
TSU:STO Stop condition
100 kHz mode
4.7
—
μs
setup time
400 kHz mode
0.6
—
μs
TAA
Output valid from 100 kHz mode
clock
400 kHz mode
—
3500 ns (Note 1)
—
—
ns
TBUF
Bus free time
100 kHz mode
400 kHz mode
4.7
—
μs Time the bus must be free
1.3
—
μs ^{before a new transmission}
can start
CB
Bus capacitive loading
—
400 pF
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I²C bus specification), before the SCL line is released.
© 2009 Microchip Technology Inc.
DS41291F-page 271