PIC16F882_09 Datasheet, PDF (30/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
TABLE 2-3: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 2
100h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 37,217
101h TMR0
Timer0 Module Register
xxxx xxxx 73,217
102h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 37,217
103h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 29,217
104h FSR
Indirect Data Memory Address Pointer
xxxx xxxx 37,217
105h WDTCON
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 225,218
106h PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xxxx 48,217
107h CM1CON0 C1ON C1OUT C1OE
C1POL
—
C1R
C1CH1 C1CH0 0000 -000 88,218
108h CM2CON0 C2ON C2OUT C2OE
C2POL
—
C2R
C2CH1 C2CH0 0000 -000 89,218
109h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL
—
—
T1GSS C2SYNC 0000 --10 91,219
10Ah PCLATH
10Bh INTCON
—
—
—
GIE
PEIE
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF⁽¹⁾
---0 0000
0000 000x
37,217
31,217
10Ch EEDAT
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 112,219
10Dh ^EEADR
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 112,219
10Eh EEDATH
—
—
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 112,219
10Fh EEADRH
—
—
—
EEADRH4⁽²⁾ EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 112,219
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
PIC16F886/PIC16F887 only.
TABLE 2-4: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 3
180h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217
181h OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 30,218
182h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 37,217
183h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 29,217
184h FSR
Indirect Data Memory Address Pointer
xxxx xxxx 37,217
185h SRCON
SR1
SR0
C1SEN C2REN PULSS PULSR
—
FVREN 0000 00-0 93,219
186h TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 48,218
187h BAUDCTL
188h ANSEL
ABDOVF RCIDL
ANS7⁽²⁾ ANS6⁽²⁾
—
ANS5⁽²⁾
SCKP
ANS4
BRG16
ANS3
—
ANS2
WUE
ANS1
ABDEN
ANS0
01-0 0-00
1111 1111
162,219
40,219
189h ANSELH
—
—
ANS13 ANS12 ANS11 ANS10 ANS9
ANS8 --11 1111 99,219
18Ah PCLATH
18Bh INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 37,217
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF⁽¹⁾ 0000 000x 31,217
18Ch EECON1
EEPGD
—
—
—
WRERR WREN
WR
RD
x--- x000 113,219
18Dh EECON2
EEPROM Control Register 2 (not a physical register)
---- ---- 111,219
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
PIC16F884/PIC16F887 only.
DS41291F-page 28
© 2009 Microchip Technology Inc.