PIC16F882_09 Datasheet, PDF (29/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
TABLE 2-2: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217
81h OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 30,218
82h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 37,217
83h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 29,217
84h FSR
Indirect Data Memory Address Pointer
xxxx xxxx 37,217
85h TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 39,218
86h TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 48,218
87h TRISC
88h TRISD⁽³⁾
89h TRISE
TRISC7
TRISD7
—
TRISC6
TRISD6
—
TRISC5
TRISD5
—
TRISC4
TRISD4
—
TRISC3
TRISD3
TRISE3
TRISC2 TRISC1 TRISC0 1111 1111
TRISD2 TRISD1 TRISD0 1111 1111
TRISE2⁽³⁾ TRISE1⁽³⁾ TRISE0⁽³⁾ ---- 1111
53,218
57,218
59,218
8Ah PCLATH
8Bh INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 37,217
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF⁽¹⁾ 0000 000x 31,217
8Ch PIE1
—
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE -000 0000 32,218
8Dh PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE ULPWUIE
—
CCP2IE 0000 00-0 33,218
8Eh PCON
—
—
ULPWUE SBOREN
—
—
POR
BOR --01 --qq 36,218
8Fh OSCCON
—
IRCF2
IRCF1
IRCF0
OSTS
HTS
LTS
SCS -110 q000 62,218
90h OSCTUNE
—
—
—
TUN4
TUN3
TUN2
TUN1
TUN0 ---0 0000 66,218
91h SSPCON2
GCEN ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
SEN 0000 0000 181,218
92h PR2
93h SSPADD⁽²⁾
93h ^SSPMSK(2)
Timer2 Period Register
Synchronous Serial Port (I²C mode) Address Register
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
1111 1111
0000 0000
1111 1111
81,218
189,218
189,218
94h SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 189,218
95h WPUB
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 49,218
96h IOCB
IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 49,218
97h VRCON
VREN
VROE
VRR
VRSS
VR3
VR2
VR1
VR0 0000 0000 97,218
98h TXSTA
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D 0000 0010 160,218
99h SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0 0000 0000 163,218
9Ah SPBRGH
BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9
BRG8 0000 0000 163,218
9Bh PWM1CON
PRSEN PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0 0000 0000 145,218
9Ch ECCPAS
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 142,218
9Dh PSTRCON
—
—
—
STRSYNC STRD
STRC
STRB
STRA ---0 0001 146,218
9Eh ADRESL
A/D Result Register Low Byte
xxxx xxxx 99,218
9Fh ADCON1
ADFM
—
VCFG1 VCFG0
—
—
—
—
0-00 ---- 105,218
Legend:
Note 1:
2:
3:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
Accessible only when SSPCON register bits SSPM<3:0> = 1001.
PIC16F884/PIC16F887 only.
© 2009 Microchip Technology Inc.
DS41291F-page 27