PIC16F882_09 Datasheet, PDF (197/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
13.4.5 BAUD RATE GENERATOR
In I²C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 13-11). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I²C Master mode, the BRG is
reloaded automatically. If clock arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 13-12).
FIGURE 13-11: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Reload
CLKOUT
BRG Down Counter
FOSC/4
FIGURE 13-12: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL
BRG
Value
BRG
Reload
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
03h
02h
01h
00h (hold off)
SCL is sampled high, reload takes
place and BRG starts its count
03h
02h
© 2009 Microchip Technology Inc.
DS41291F-page 195