PIC16F882_09 Datasheet, PDF (196/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
13.4.4.1 I²C™ Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I²C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted eight bits at a time. After each byte is trans-
mitted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received eight bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
The Baud Rate Generator used for the SPI mode oper-
ation is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I²C operation. The
Baud Rate Generator reload value is contained in the
lower 7 bits of the SSPADD register. The Baud Rate
Generator will automatically begin counting on a write
to the SSPBUF. Once the given operation is complete
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.
A typical transmit sequence would go as follows:
a) The user generates a Start condition by setting
the Start Enable (SEN) bit (SSPCON2 register).
b) SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
c) The user loads the SSPBUF with the address to
transmit.
d) Address is shifted out the SDA pin until all eight
bits are transmitted.
e) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
f) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
g) The user loads the SSPBUF with eight bits of
data.
h) Data is shifted out the SDA pin until all eight bits
are transmitted.
i) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
k) The user generates a Stop condition by setting
the Stop Enable bit PEN (SSPCON2 register).
l) Interrupt is generated once the Stop condition is
complete.
DS41291F-page 194
© 2009 Microchip Technology Inc.