PIC18F452-IPT Datasheet, PDF (73/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
7.0 8 X 8 HARDWARE MULTIPLIER
7.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX2 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 7-1: PERFORMANCE COMPARISON
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Multiply Method
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Program
Memory
(Words)
13
1
33
6
21
24
52
36
Cycles
(Max)
69
1
91
6
242
24
254
36
Time
@ 40 MHz @ 10 MHz @ 4 MHz
6.9 μs
100 ns
9.1 μs
600 ns
24.2 μs
2.4 μs
25.4 μs
3.6 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
96.8 μs
9.6 μs
102.6 μs
14.4 μs
69 μs
1 μs
91 μs
6 μs
242 μs
24 μs
254 μs
36 μs
7.2 Operation
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 7-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 =
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 2¹⁶) +
(ARG1H • ARG2L • 2⁸) +
(ARG1L • ARG2H • 2⁸) +
(ARG1L • ARG2L)
© 2006 Microchip Technology Inc.
DS39564C-page 71