PIC18F452-IPT Datasheet, PDF (65/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
Required MOVWF
Sequence MOVLW
MOVWF
BSF
BSF
DECFSZ
BRA
BCF
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
COUNTER_HI
PROGRAM_LOOP
EECON1,WREN
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; disable interrupts
; write 55h
; write AAh
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
5.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected RESET, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset, or a WDT
Time-out Reset during normal operation. In these situ-
ations, users can check the WRERR bit and rewrite the
location.
5.5.4
PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to FLASH program
memory, the write initiate sequence must also be fol-
lowed. See “Special Features of the CPU”
(Section 19.0) for more detail.
5.6 FLASH Program Operation During
Code Protection
See “Special Features of the CPU” (Section 19.0) for
details on code protection of FLASH program memory.
TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Value on:
POR, BOR
Value on
All Other
RESETS
FF8h
FF7h
FF6h
FF5h
FF2h
FA7h
FA6h
FA2h
TBLPTRU —
—
bit21 Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
TABLAT Program Memory Table Latch
INTCON
GIE/
GIEH
PEIE/ TMR0IE INTE
GIEL
RBIE TMR0IF INTF
RBIF
EECON2 EEPROM Control Register2 (not a physical register)
EECON1 EEPGD CFGS — FREE WRERR WREN WR
RD
IPR2
—
—
—
EEIP BCLIP LVDIP TMR3IP CCP2IP
--00 0000 --00 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
—
—
xx-0 x000 uu-0 u000
---1 1111 ---1 1111
FA1h PIR2
—
—
—
EEIF BCLIF LVDIF TMR3IF
FA0h PIE2
—
—
— EEIE BCLIE LVDIE TMR3IE
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
CCP2IF
CCP2IE
---0 0000 ---0 0000
---0 0000 ---0 0000
© 2006 Microchip Technology Inc.
DS39564C-page 63