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PIC18F452-IPT Datasheet, PDF (281/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D | |||
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PIC18FXX2
FIGURE 22-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
bit6 - - - - - -1
75, 76
SDI
MSb In
bit6 - - - -1
74
Note: Refer to Figure 22-4 for load conditions.
LSb
LSb In
TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 â
40
â
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 â
40
â
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
â
73A TB2B
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 â
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
â
75
TdoR
SDO data output rise time
PIC18FXXX
â
25
PIC18LFXXX
â
60
76
TdoF
SDO data output fall time
PIC18FXXX
â
25
PIC18LFXXX
â
60
78
TscR
SCK output rise time (Master mode) PIC18FXXX
â
25
PIC18LFXXX
â
60
79
TscF
SCK output fall time (Master mode) PIC18FXXX
â
25
PIC18LFXXX
â
60
80
TscH2doV, SDO data output valid after SCK PIC18FXXX
TscL2doV edge
PIC18LFXXX
â
50
â
150
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
â
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
© 2006 Microchip Technology Inc.
DS39564C-page 279
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