PIC18F452-IPT Datasheet, PDF (282/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
FIGURE 22-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
83
78
79
80
79
78
SDO
MSb
bit6 - - - - - -1
LSb
SDI
Note:
75, 76
MSb In
74
73
Refer to Figure 22-4 for load conditions.
bit6 - - - -1
77
LSb In
TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Param. No. Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
71
TscH
SCK input high time (Slave mode)
Continuous 1.25 TCY + 30 —
71A
Single Byte
40
—
72
TscL
SCK input low time (Slave mode)
Continuous 1.25 TCY + 30 —
72A
Single Byte
40
—
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
—
73A
TB2B
Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 —
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time
PIC18FXXX
—
25
PIC18LFXXX
—
60
76
TdoF
SDO data output fall time
PIC18FXXX
—
25
PIC18LFXXX
—
60
77
TssH2doZ SS↑ to SDO output hi-impedance
10
50
78
TscR
SCK output rise time (Master mode) PIC18FXXX
—
25
PIC18LFXXX
—
60
79
TscF
SCK output fall time (Master mode) PIC18FXXX
—
25
PIC18LFXXX
—
60
80
TscH2doV, SDO data output valid after SCK edge PIC18FXXX
—
50
TscL2doV
PIC18LFXXX
—
150
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
DS39564C-page 280
© 2006 Microchip Technology Inc.