PIC18F452-IPT Datasheet, PDF (280/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
FIGURE 22-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
78
79
SDO
80
MSb
79
78
bit6 - - - - - -1
LSb
75, 76
SDI
MSb In
bit6 - - - -1
74
73
Note: Refer to Figure 22-4 for load conditions.
LSb In
TABLE 22-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
—
73A TB2B
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 —
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time
PIC18FXXX
—
25
PIC18LFXXX
—
60
76
TdoF
SDO data output fall time
PIC18FXXX
—
25
PIC18LFXXX
—
60
78
TscR
SCK output rise time
(Master mode)
PIC18FXXX
PIC18LFXXX
—
25
—
60
79
TscF
SCK output fall time (Master mode) PIC18FXXX
—
25
PIC18LFXXX
—
60
80
TscH2doV, SDO data output valid after SCK PIC18FXXX
TscL2doV edge
PIC18LFXXX
—
50
—
150
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
ns VDD = 2V
ns
ns VDD = 2V
DS39564C-page 278
© 2006 Microchip Technology Inc.