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PIC18F452-IPT Datasheet, PDF (224/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D | |||
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PIC18FXX2
BNOV
Branch if Not Overflow
Syntax:
[ label ] BNOV n
Operands:
-128 ⤠n ⤠127
Operation:
if overflow bit is â0â
(PC) + 2 + 2n â PC
Status Affected: None
Encoding:
1110 0101 nnnn nnnn
Description:
If the Overflow bit is â0â, then the
program will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
Read literal
'n'
No
operation
Process
Data
No
operation
Write to PC
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BNOV Jump
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
BNZ
Branch if Not Zero
Syntax:
[ label ] BNZ n
Operands:
-128 ⤠n ⤠127
Operation:
if zero bit is â0â
(PC) + 2 + 2n â PC
Status Affected: None
Encoding:
1110 0001 nnnn nnnn
Description:
If the Zero bit is â0â, then the pro-
gram will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
Read literal
'n'
No
operation
Process
Data
No
operation
Write to PC
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Zero
=
PC
=
If Zero
=
PC
=
BNZ Jump
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
DS39564C-page 222
© 2006 Microchip Technology Inc.
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