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| PIC18F452-IPT Datasheet, PDF (30/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D | |||
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PIC18FXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
TOSH
242 442 252 452
242 442 252 452
---0 0000
0000 0000
---0 0000
0000 0000
---0 uuuu(3)
uuuu uuuu(3)
TOSL
242 442 252 452
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
242 442 252 452
00-0 0000
uu-0 0000
uu-u uuuu(3)
PCLATU
242 442 252 452
---0 0000
---0 0000
---u uuuu
PCLATH
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
PCL
242 442 252 452
0000 0000
0000 0000
PC + 2(2)
TBLPTRU 242 442 252 452
--00 0000
--00 0000
--uu uuuu
TBLPTRH 242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TBLPTRL 242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TABLAT
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
PRODH
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
242 442 252 452
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
INTCON3
242 442 252 452
242 442 252 452
1111 -1-1
11-0 0-00
1111 -1-1
11-0 0-00
uuuu -u-u(1)
uu-u u-uu(1)
INDF0
242 442 252 452
N/A
N/A
N/A
POSTINC0 242 442 252 452
N/A
N/A
N/A
POSTDEC0 242 442 252 452
N/A
N/A
N/A
PREINC0 242 442 252 452
N/A
N/A
N/A
PLUSW0 242 442 252 452
N/A
N/A
N/A
FSR0H
242 442 252 452
---- xxxx
---- uuuu
---- uuuu
FSR0L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
242 442 252 452
N/A
N/A
N/A
POSTINC1 242 442 252 452
N/A
N/A
N/A
POSTDEC1 242 442 252 452
N/A
N/A
N/A
PREINC1 242 442 252 452
N/A
N/A
N/A
PLUSW1 242 442 252 452
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read â0â.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read â0â.
DS39564C-page 28
© 2006 Microchip Technology Inc.
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