PIC18F2220 Datasheet, PDF (65/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0 0000 q000 26, 47
LVDCON
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0 --00 0101 47, 233
WDTCON
—
—
—
—
—
—
—
SWDTEN --- ---0 47, 246
RCON
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 11q0 45, 69, 98
TMR1H
Timer1 Register High Byte
xxxx xxxx 47, 125
TMR1L
Timer1 Register Low Byte
xxxx xxxx 47, 125
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 47, 121
TMR2
Timer2 Register
0000 0000 47, 127
PR2
Timer2 Period Register
1111 1111 47, 127
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 47, 127
SSPBUF
SSPADD
SSP Receive Buffer/Transmit Register
SSP Address Register in I²C Slave mode. SSP Baud Rate Reload Register in I²C Master mode.
xxxx xxxx
0000 0000
47, 156,
164
47, 164
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 47, 156,
165
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 47, 157,
166
SSPCON2
GCEN ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000 47, 167
ADRESH
A/D Result Register High Byte
xxxx xxxx 48, 220
ADRESL
A/D Result Register Low Byte
xxxx xxxx 48, 220
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON --00 0000 48, 211
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0 --00 0000 48, 212
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0-00 0000 48, 213
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 48, 134
CCPR1L
CCP1CON
Capture/Compare/PWM Register 1 Low Byte
P1M1⁽⁵⁾
P1M0⁽⁵⁾
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
xxxx xxxx
0000 0000
48, 134
48, 133,
141
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 48, 134
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 48, 134
CCP2CON
PWM1CON⁽⁵⁾
ECCPAS⁽⁵⁾
—
PRSEN
ECCPASE
—
PDC6
ECCPAS2
DC2B1
PDC5
ECCPAS1
DC2B0
PDC4
ECCPAS0
CCP2M3
PDC3
PSSAC1
CCP2M2
PDC2
PSSAC0
CCP2M1
PDC1
PSSBD1
CCP2M0
PDC0
PSSBD0
--00 0000
0000 0000
0000 0000
48, 133
48, 149
48, 150
CVRCON
CVREN CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0 000- 0000 48, 227
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111 48, 221
TMR3H
Timer3 Register High Byte
xxxx xxxx 48, 131
TMR3L
Timer3 Register Low Byte
xxxx xxxx 48, 131
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 48, 129
SPBRG
USART Baud Rate Generator
0000 0000 48, 198
RCREG
USART Receive Register
0000 0000 48, 204,
203
TXREG
USART Transmit Register
0000 0000 48, 202,
203
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 48, 196
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 48, 197
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is
read-only.
 2003 Microchip Technology Inc.
DS39599C-page 63