PIC18F2220 Datasheet, PDF (47/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up⁽²⁾ and Brown-out
PWRTEN = 0
PWRTEN = 1
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
66 ms⁽¹⁾ + 1024 TOSC + 2 ms⁽²⁾
66 ms⁽¹⁾ + 1024 TOSC
66 ms⁽¹⁾
66 ms⁽¹⁾
66 ms⁽¹⁾
1024 TOSC + 2 ms⁽²⁾
1024 TOSC
—
—
—
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the 4x PLL to lock.
Exit from
Power Managed Mode
1024 TOSC + 2 ms⁽²⁾
1024 TOSC
—
—
—
REGISTER 4-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
U-0
U-0
R/W-1
R-1
IPEN
—
—
RI
TO
bit 7
R-1
R/W-1
PD
POR
Note: Refer to Section 5.14 “RCON Register” for bit definitions.
R/W-1
BOR
bit 0
TABLE 4-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter
RCON
Register
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
RESET Instruction
Brown-out
0000h 0--1 1100 1 1 1 0
0
0
0
0000h 0--0 uuuu 0 u u u
u
u
u
0000h 0--1 11u- 1 1 1 u
0
u
u
MCLR during power managed
Run modes
0000h 0--u 1uuu u 1 u u
u
u
u
MCLR during power managed
Idle modes and Sleep mode
0000h 0--u 10uu u 1 0 u
u
u
u
WDT Time-out during full power
or power managed Run mode
0000h
0--u 0uuu u 0 u
u
u
u
u
MCLR during full power
execution
u
u
Stack Full Reset (STVREN = 1) 0000h 0--u uuuu u u u u
u
1
u
Stack Underflow Reset
(STVREN = 1)
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h u--u uuuu u u u u
u
u
1
WDT Time-out during power
managed Idle or Sleep modes
PC + 2 u--u 00uu u 0 0 u
u
u
u
Interrupt exit from power
managed modes
PC + 2 u--u u0uu u u 0 u
u
u
u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
 2003 Microchip Technology Inc.
DS39599C-page 45