PIC18F2220 Datasheet, PDF (109/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
10.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input buff-
ers. RC1 is normally configured by configuration bit,
CCP2MX (CONFIG3H<0>), as the default peripheral
pin of the CCP2 module (default/erased state,
CCP2MX = 1).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
CLRF PORTC
CLRF LATC
MOVLW 0xCF
MOVWF TRISC
INITIALIZING PORTC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
FIGURE 10-10:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select⁽²⁾
VDD
Peripheral Data Out
RD LATC
Data Bus
WR LATC or
WR PORTC
WR TRISC
RD TRISC
Peripheral Output
Enable⁽³⁾
0
DQ
CK Q
1
Data Latch
DQ
CK Q
TRIS Latch
P
I/O pin⁽¹⁾
N
Schmitt
VSS
Trigger
Q
D
EN
RD PORTC
Peripheral Data In
Note 1:
2:
3:
I/O pins have diode protection to VDD and VSS.
Port/Peripheral Select signal selects between port data (output) and peripheral output.
Peripheral Output Enable is only active if Peripheral Select is active.
 2003 Microchip Technology Inc.
DS39599C-page 107