PIC18F2220 Datasheet, PDF(222/388 Page) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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PIC18F2220 Datasheet, PDF (222/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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PIC18F2220/2320/4220/4320

19.8 Use of the CCP2 Trigger

An A/D conversion can be started by the âspecial event

triggerâ of the CCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-

grammed as â1011â and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the GO/

DONE bit will be set, starting the A/D acquisition and

conversion and the Timer1 (or Timer3) counter will be

reset to zero. Timer1 (or Timer3) is reset to automati-

cally repeat the A/D acquisition period with minimal

software overhead (moving ADRESH/ADRESL to the

desired location). The appropriate analog input chan-

nel must be selected and the minimum acquisition

period is either timed by the user or an appropriate

TACQ time, selected before the âspecial event triggerâ,

sets the GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared), the

âspecial event triggerâ will be ignored by the A/D

module but will still reset the Timer1 (or Timer3)

counter.

TABLE 19-2: SUMMARY OF A/D REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE

GIEL

RBIE TMR0IF INT0IF

RBIF 0000 0000 0000 0000

PIR1

PSPIF

ADIF

RCIF

TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111

PIR2

OSCFIF CMIF

â

EEIF BCLIF LVDIF TMR3IF CCP2IF 00-0 0000 00-0 0000

PIE2

OSCFIE CMIE

â

EEIE BCLIE LVDIE TMR3IE CCP2IE 00-0 0000 00-0 0000

IPR2

OSCFIP CMIP

â

EEIP BCLIP LVDIP TMR3IP CCP2IP 11-1 1111 11-1 1111

ADRESH A/D Result Register High Byte

xxxx xxxx uuuu uuuu

ADRESL A/D Result Register Low Byte

xxxx xxxx uuuu uuuu

ADCON0

â

â

CHS3 CHS3 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

ADCON1

â

â

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 qqqq --00 qqqq

ADCON2

PORTA

TRISA

ADFM

â

RA7(4)

RA6(4)

TRISA7(4) TRISA6(4)

ACQT2

RA5

ACQT1 ACQT0 ADCS2

RA4

RA3

RA2

ADCS1

RA1

ADCS0

RA0

0-00 0000

--0x 0000

--11 1111

0-00 0000

--0u 0000

--11 1111

PORTB Read PORTB pins, Write LATB Latch

xxxx xxxx uuuu uuuu

TRISB PORTB Data Direction Register

1111 1111 1111 1111

LATB

PORTE

TRISE(3)

LATE(3)

PORTB Output Data Latch

â

â

â

IBF

OBE

IBOV

â

â

â

xxxx xxxx

â

RE3(2) Read PORTE pins, Write LATE(4) ---- xxxx

PSPMODE â PORTE Data Direction

0000 -111

â PORTE Output Data Latch

---- -xxx

uuuu uuuu

---- uuuu

0000 -111

---- -uuu

Legend:

Note 1:

2:

3:

4:

x = unknown, u = unchanged, - = unimplemented, read as â0â, q = value depends on condition.

Shaded cells are not used for A/D conversion.

RE3 port bit is available only as an input pin when MCLRE bit in configuration register is â0â.

This register is not implemented on PIC18F2X20 devices.

These bits are not implemented on PIC18F2X20 devices.

These pins may be configured as port pins depending on the oscillator mode selected.

DS39599C-page 220

ï£© 2003 Microchip Technology Inc.

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