PIC18F2220 Datasheet, PDF (124/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the Clock Select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. The TRISC1:TRISC0 values are
ignored and the pins read as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
TMR1IF
Overflow
Interrupt
Flag bit
T1CKI/T1OSO
T1OSI
CCP Special Event Trigger
TMR1
CLR
TMR1H TMR1L
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
TMR1ON
On/Off
1
FOSC/4
Internal 0
Clock
0
Synchronized
Clock Input
1
T1SYNC
Prescaler
1, 2, 4, 8
Synchronize
det
2
Peripheral Clocks
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
T1CKI/T1OSO
T1OSI
8
TMR1
Timer 1
High Byte
CLR
TMR1L
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
Synchronized
0
Clock Input
TMR1ON
on/off
1
T1SYNC
1
FOSC/4
Internal
Clock
0
TMR1CS
Prescaler
1, 2, 4, 8
2
Synchronize
det
Peripheral Clocks
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39599C-page 122
 2003 Microchip Technology Inc.