PIC18F2220 Datasheet, PDF (249/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
23.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscil-
lator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
Two-Speed Start-up is available only if the primary oscil-
lator mode is LP, XT, HS or HSPLL (Crystal-based
modes). Other sources do not require a OST start-up
delay; for these, Two-Speed Start-up is disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execution
while the primary oscillator starts and the OST is run-
ning. Once the OST times out, the device automatically
switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits IFRC2:IFRC0 immediately after
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
In all other power managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
23.3.1 SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power managed modes, including serial
SLEEP instructions (refer to Section 3.1.3 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings and issue
SLEEP commands before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
FIGURE 23-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
INTOSC
Multiplexer
OSC1
PLL Clock
Output
Q1
Q2
Q3
Q4 Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST⁽¹⁾
TPLL⁽¹⁾
12345678
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
PC + 6
Wake from Interrupt Event
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
 2003 Microchip Technology Inc.
DS39599C-page 247