PIC18F2220 Datasheet, PDF (291/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f (no carry)
[ label ] RRNCF f [,d [,a]]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n-1>,
(f<0>) → dest<7>
N, Z
0100 00da ffff ffff
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed back in reg-
ister ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example 1:
RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:
RRNCF REG, W
Before Instruction
W
REG
=?
= 1101 0111
After Instruction
W
REG
= 1110 1011
= 1101 0111
SETF
Set f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
[ label ] SETF f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
FFh → f
None
0110 100a ffff ffff
The contents of the specified regis-
ter are set to FFh. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
1
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
SETF
Before Instruction
REG
=
After Instruction
REG
=
REG
0x5A
0xFF
 2003 Microchip Technology Inc.
DS39599C-page 289