PIC18F2220 Datasheet, PDF (115/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
TABLE 10-9: PORTE FUNCTIONS
Name
Bit# Buffer Type
Function
RE0/AN5/RD
bit 0
ST/TTL⁽¹⁾ Input/output port pin, analog input or read control input in Parallel Slave
Port mode.
For RD (PSP Control mode):
1 = PSP is Idle
0 = Read operation. Reads PORTD register (if chip selected).
RE1/AN6/WR
bit 1
ST/TTL⁽¹⁾ Input/output port pin, analog input or write control input in Parallel
Slave Port mode.
For WR (PSP Control mode):
1 = PSP is Idle
0 = Write operation. Writes PORTD register (if chip selected).
RE2/AN7/CS
bit 2
ST/TTL⁽¹⁾ Input/output port pin, analog input or chip select control input in Parallel
Slave Port mode.
For CS (PSP Control mode):
1 = PSP is Idle
0 = External device is selected
MCLR/VPP/RE3 bit 3
ST
Input only port pin or programming voltage input (if MCLR is disabled);
Master Clear input or programming voltage input (if MCLR is enabled).
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
PORTE
LATE
TRISE
ADCON1
Legend:
Note 1:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
—
—
—
—
RE3⁽¹⁾
RE2
RE1
RE0 ---- q000
—
—
—
—
— LATE Data Latch Register
---- -xxx
IBF
OBF
IBOV PSPMODE — PORTE Data Direction bits
0000 -111
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used by PORTE.
Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0).
Value on
all other
Resets
---- q000
---- -uuu
0000 -111
--00 0000
 2003 Microchip Technology Inc.
DS39599C-page 113