PIC18F2220 Datasheet, PDF (111/388 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
10.4 PORTD, TRISD and LATD
Registers
Note: PORTD is only available on PIC18F4X20
devices.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory mapped.
Read-modify-write operations on the LATD register read
and write the latched output value for PORTD.
All pins on PORTD are implemented with Schmitt Trig-
ger input buffers. Each pin is individually configurable
as an input or output.
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.6 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
Note:
When the enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
EXAMPLE 10-4: INITIALIZING PORTD
CLRF PORTD
CLRF LATD
MOVLW 0xCF
MOVWF TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
: Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
FIGURE 10-11: BLOCK DIAGRAM OF RD7:RD5 PINS
PORTD/CCP1 Select
CCP Data Out
PSPMODE
RD LATD
Data Bus
WR LATD
or PORTD
WR TRISD
PSP Read
RD TRISD
D
Q
CK Q
Data Latch
DQ
CK Q
TRIS Latch
0
1
0
1
Q
D
RD PORTD
0
ENEN
PSP Write
1
Note 1: I/O pins have diode protection to VDD and VSS.
VDD
P
N
VSS
TTL Buffer
1
I/O pin⁽¹⁾
0
Schmitt Trigger
Input Buffer
 2003 Microchip Technology Inc.
DS39599C-page 109