70592C Datasheet, PDF (65/314 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJXXXGPX06A/X08A/X10A
REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0⁽¹⁾
R/W-0⁽¹⁾
R/W-0⁽¹⁾
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
bit 15
U-0
—
bit 7
R/W-0⁽¹⁾
U-0
ERASE
—
U-0
R/W-0⁽¹⁾
R/W-0⁽¹⁾
R/W-0⁽¹⁾
—
NVMOP<3:0>⁽²⁾
U-0
—
bit 8
R/W-0⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
SO = Settable only bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits⁽²⁾
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)
1110 = Reserved
1101 = Erase General Segment and FGS Configuration Register
(ERASE = 1) or no operation (ERASE = 0)
1100 = Erase Secure Segment and FSS Configuration Register
(ERASE = 1) or no operation (ERASE = 0)
1011 = Reserved
•
•
•
0100 = Reserved
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
0000 = Program or erase a single Configuration register byte
Note 1: These bits can only be reset on a POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
© 2011 Microchip Technology Inc.
DS70592C-page 65