70592C Datasheet, PDF (117/314 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJXXXGPX06A/X08A/X10A
8.0 DIRECT MEMORY ACCESS
(DMA)
Note 1: This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the infor-
mation in this data sheet, refer to Section
22. “Direct Memory Access (DMA)”
(DS70223) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU intervention. The DMA controller can
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and, therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The PIC24HJXXXGPX06A/X08A/X10A peripherals
that can utilize DMA are listed in Table 8-1 along with
their associated Interrupt Request (IRQ) numbers.
TABLE 8-1: PERIPHERALS WITH DMA
SUPPORT
Peripheral
IRQ Number
INT0
0
Input Capture 1
1
Input Capture 2
5
Output Compare 1
2
Output Compare 2
6
Timer2
7
Timer3
8
SPI1
10
SPI2
33
UART1 Reception
11
UART1 Transmission
12
UART2 Reception
30
UART2 Transmission
31
ADC1
13
ADC2
21
ECAN1 Reception
34
ECAN1 Transmission
70
ECAN2 Reception
55
ECAN2 Transmission
71
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Word or byte sized data transfers
• Transfers from peripheral to DMA RAM or DMA
RAM to peripheral
• Indirect Addressing of DMA RAM locations with or
without automatic post-increment
• Peripheral Indirect Addressing – In some
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral
• One-Shot Block Transfers – Terminating DMA
transfer after one block transfer
• Continuous Block Transfers – Reloading DMA RAM
buffer start address after every block transfer is
complete
• Ping-Pong Mode – Switching between two DMA
RAM start addresses between successive block
transfers, thereby filling two buffers alternately
• Automatic or manual initiation of block transfers
• Each channel can select from 19 possible sources
of data sources or destinations
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete. Alterna-
tively, an interrupt can be generated when half of the
block has been filled.
© 2011 Microchip Technology Inc.
DS70592C-page 117