70592C Datasheet, PDF (221/314 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJXXXGPX06A/X08A/X10A
21.0 SPECIAL FEATURES
Note 1: This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
families of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the infor-
mation in this data sheet, refer to Section
23.
“CodeGuard™
Security”
(DS70239), Section 24. “Programming
and Diagnostics” (DS70246), and Sec-
tion 25. “Device Configuration”
(DS70231) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
PIC24HJXXXGPX06A/X08A/X10A devices include
several features intended to maximize application flex-
ibility and reliability, and minimize cost through elimina-
tion of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• In-Circuit Emulation
21.1 Configuration Bits
PIC24HJXXXGPX06A/X08A/X10A devices provide
nonvolatile memory implementation for device
configuration bits. Refer to Section 25. “Device Con-
figuration” (DS70194) of the “dsPIC33F/PIC24H
Family Reference Manual”, for more information on this
implementation.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 21-1.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 21-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
TABLE 21-1: DEVICE CONFIGURATION REGISTER MAP
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
0xF80000 FBS
RBS<1:0>
—
—
BSS<2:0>
BWRP
0xF80002 FSS
RSS<1:0>
—
—
SSS<2:0>
SWRP
0xF80004 FGS
—
—
—
—
—
0xF80006 FOSCSEL IESO Reserved⁽²⁾
—
—
—
GSS<1:0>
GWRP
FNOSC<2:0>
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
FCKSM<1:0>
—
FWDTEN WINDIS PLLKEN⁽³⁾
Reserved⁽⁴⁾
Reserved⁽¹⁾
JTAGEN
—
WDTPRE
—
—
— OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
—
FPWRT<2:0>
—
—
ICS<1:0>
0xF80010 FUID0
User Unit ID Byte 0
0xF80012 FUID1
User Unit ID Byte 1
0xF80014 FUID2
User Unit ID Byte 2
0xF80016 FUID3
User Unit ID Byte 3
Legend: — = unimplemented bits, read as ‘0’.
Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’.
2: When read, this bit returns the current programmed value.
3: This bit is unimplemented on PIC24HJ64GPX06A/X08A/X10A and PIC24HJ128GPX06A/X08A/X10A
devices and reads as ‘0’.
4: These bits are reserved and always read as ‘1’.
© 2011 Microchip Technology Inc.
DS70592C-page 221