70592C Datasheet, PDF (224/314 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJXXXGPX06A/X08A/X10A
TABLE 21-2: PIC24HJXXXGPX06A/X08A/X10A CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
RTSP
Effect
Description
IESO
FNOSC<2:0>
FCKSM<1:0>
OSCIOFNC
POSCMD<1:0>
FWDTEN
FOSCSEL
FOSCSEL
FOSC
FOSC
FOSC
FWDT
Immediate
If clock
switch is
enabled,
RTSP
effect is on
any device
Reset;
otherwise,
Immediate
Immediate
Immediate
Immediate
Immediate
Internal External Start-up Option bit
1 = Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0 = Start-up device with user-selected oscillator source
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) oscillator with postscaler
110 = Reserved
101 = LPRC oscillator
100 = Secondary (LP) oscillator
011 = Primary (XT, HS, EC) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRC) oscillator with PLL
000 = FRC oscillator
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
Primary Oscillator Mode Select bits
11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
PLLKEN
WDTPRE
WDTPOST
FWDT
FWDT
FWDT
FWDT
Immediate Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
Immediate PLL Lock Enable bit
1 = Clock switch to PLL source will wait until the PLL lock signal is valid.
0 = Clock switch will not wait for the PLL lock signal.
Immediate Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
Immediate Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
.
.
.
0001 = 1:2
0000 = 1:1
DS70592C-page 224
© 2011 Microchip Technology Inc.