70592C Datasheet, PDF (205/314 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-26: CiTRmnCON: ECAN™ MODULE TX/RX BUFFER m CONTROL REGISTER
(m = 0,2,4,6; n = 1,3,5,7)
R/W-0
TXENn
bit 15
R-0
TXABTn
R-0
TXLARBn
R-0
TXERRn
R/W-0
TXREQn
R/W-0
RTRENn
R/W-0
R/W-0
TXnPRI<1:0>
bit 8
R/W-0
TXENm
bit 7
R-0
R-0
R-0
R/W-0
TXABTm⁽¹⁾ TXLARBm⁽¹⁾ TXERRm⁽¹⁾ TXREQm
R/W-0
RTRENm
R/W-0
R/W-0
TXmPRI<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
See Definition for Bits 7-0, Controls Buffer n
TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
TXABTm: Message Aborted bit⁽¹⁾
1 = Message was aborted
0 = Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit⁽¹⁾
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit⁽¹⁾
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when the message
is successfully sent. Clearing the bit to ‘0’ while set will request a message abort.
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1: This bit is cleared when TXREQ is set.
© 2011 Microchip Technology Inc.
DS70592C-page 205