70592C Datasheet, PDF (167/314 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJXXXGPX06A/X08A/X10A
17.0 INTER-INTEGRATED
CIRCUIT™ (I²C™)
Note 1: This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 19. “Inter-Integrated Circuit™
(I²C™)” (DS70235) of the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip
website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Inter-Integrated Circuit (I²C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I²C serial communication
standard, with a 16-bit interface.
The PIC24HJXXXGPX06A/X08A/X10A devices have
up to two I²C interface modules, denoted as I2C1 and
I2C2. Each I²C module has a 2-pin interface: the SCLx
pin is clock and the SDAx pin is data.
Each I²C module ‘x’ (x = 1 or 2) offers the following key
features:
• I²C interface supporting both master and slave
operation
• I²C Slave mode supports 7-bit and 10-bit
addressing
• I²C Master mode supports 7-bit and 10-bit
addressing
• I²C Port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I²C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
• I²C supports multi-master operation; detects bus
collision and will arbitrate accordingly
17.1 Operating Modes
The hardware fully implements all the master and slave
functions of the I²C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
The I²C module can operate either as a slave or a
master on an I²C bus.
The following types of I²C operation are supported:
• I²C slave operation with 7-bit addressing
• I²C slave operation with 10-bit addressing
• I²C master operation with 7-bit or 10-bit addressing
For details about the communication sequence in each
of these modes, please refer to the “dsPIC33F/PIC24H
Family Reference Manual”.
17.2 I²C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-bit Address mode. The
I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
© 2011 Microchip Technology Inc.
DS70592C-page 167