70592C Datasheet, PDF (118/314 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJXXXGPX06A/X08A/X10A
FIGURE 8-1:
SRAM
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
Peripheral Indirect Address
DMA Controller
DMA RAM
PORT 1 PORT 2
DMA
Channels
DMA
Ready
Peripheral 3
CPU DMA
SRAM X-Bus
DMA DS Bus
CPU Peripheral DS Bus
CPU
Non-DMA
Ready
Peripheral
Note: CPU and DMA address buses are not shown for clarity.
8.1 DMAC Registers
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
(DMAxCON)
• A 16-bit DMA Channel IRQ Select register
(DMAxREQ)
• A 16-bit DMA RAM Primary Start Address Offset
register (DMAxSTA)
• A 16-bit DMA RAM Secondary Start Address
Offset register (DMAxSTB)
• A 16-bit DMA Peripheral Address register
(DMAxPAD)
• A 10-bit DMA Transfer Count register (DMAx-
CNT)
An additional pair of status registers, DMACS0 and
DMACS1 are common to all DMAC channels.
CPU DMA
DMA
Ready
Peripheral 1
CPU DMA
DMA
Ready
Peripheral 2
DS70592C-page 118
© 2011 Microchip Technology Inc.