70592C Datasheet, PDF (153/314 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJXXXGPX06A/X08A/X10A
REGISTER 13-2: TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
TON⁽¹⁾
—
TSIDL⁽²⁾
—
—
—
—
bit 15
U-0
—
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
—
TGATE⁽¹⁾
TCKPS<1:0>⁽¹⁾
—
bit 7
U-0
R/W-0
U-0
—
TCS^(1,3)
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-2
bit 1
bit 0
TON: Timery On bit⁽¹⁾
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit⁽²⁾
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
TGATE: Timery Gated Time Accumulation Enable bit⁽¹⁾
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
TCKPS<1:0>: Timer3 Input Clock Prescale Select bits⁽¹⁾
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
Unimplemented: Read as ‘0’
TCS: Timery Clock Source Select bit^(1,3)
1 = External clock from pin TyCK (on the rising edge)
0 = Internal clock (FCY)
Unimplemented: Read as ‘0’
Note 1:
2:
3:
When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through T2CON.
When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
The TyCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.
© 2011 Microchip Technology Inc.
DS70592C-page 153