PIC16F1946 Datasheet, PDF (372/440 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16F/LF1946/47
TABLE 28-3: PIC16F/LF1946/47 ENHANCED INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
14-Bit Opcode
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
k
BRW
–
CALL
k
CALLW –
GOTO k
RETFIE k
RETLW k
RETURN –
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
11
2
00
2
10
2
00
2
10
2
00
2
11
2
00
INHERENT OPERATIONS
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
CLRWDT –
NOP
–
OPTION –
RESET –
SLEEP –
TRIS
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
00
1
00
1
00
1
00
1
00
1
00
C-COMPILER OPTIMIZED
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100
0000
0010
0001
0011
0fff
TO, PD
TO, PD
ADDFSR n, k
Add Literal k to FSR, n = FSR0 or FSR1
1
11 0001 0nkk kkkk
MOVIW n
Move Indirect to W, n = FSR0 or FSR1, with 1
00 0000 0001 0nmm Z
2
pre/post inc/dec modifier.
1
11 1111 0nkk kkkk Z
2
MOVWI k[n]
Move INDFn to W, Indexed Indirect.
1
00 0000 0001 1nmm
2
n
Move W to Indirect, n = FSR0 or FSR1, with 1
11 1111 1nkk kkkk
2
pre/post inc/dec modifier.
k[n]
Move W to INDFn, Indexed Indirect.
Note 1:
2:
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
DS41414A-page 370
Preliminary
 2010 Microchip Technology Inc.