PIC16F1946 Datasheet, PDF (291/440 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16F/LF1946/47
24.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
Note:
The PIC16F/LF/1946/47 devices have two
EUSARTs. Therefore, all information in
this section refers to both EUSART 1 and
EUSART 2.
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock and data polarity
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 24-1 and Figure 24-2.
FIGURE 24-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXxREG Register
MSb
8
LSb
(8)
•••
0
Transmit Shift Register (TSR)
TXxIE
TXxIF
Pin Buffer
and Control
Interrupt
TXx/CKx pin
TXEN
Baud Rate Generator
BRG16
+1
SPxBRGH SPxBRGL
FOSC
÷n
n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
TX9
TX9D
TRMT
 2010 Microchip Technology Inc.
Preliminary
DS41414A-page 289