PIC16F1946 Datasheet, PDF (213/440 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16F/LF1946/47
22.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCPxCON
PxM<1:0>⁽¹⁾
DCxB<1:0>
CCPxM<3:0>
CCPRxL Capture/Compare/PWM Register x Low Byte (LSB)
CCPRxH Capture/Compare/PWM Register x High Byte (MSB)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
—
CCP2IE
PIE3
—
CCP5IE CCP4IE CCP3IE
TMR6IE
—
TMR4IE
—
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
—
CCP2IF
PIR3
—
CCP5IF CCP4IF CCP3IF
TMR6IF
—
TMR4IF
—
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN T1SYNC
—
TMR1ON
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA
TRISA7 TRISA6 TRISA5 TRISA4
TRISA3
TRISA2 TRISA1 TRISA0
TRISB
TRISB7 TRISB6 TRISB5 TRISB4
TRISB3
TRISB2 TRISB1 TRISB0
TRISC
TRISC7 TRISC6 TRISC5 TRISC4
TRISC3
TRISC2 TRISC1 TRISC0
TRISD
TRISD7 TRISD6 TRISD5 TRISD4
TRISD3
TRISD2 TRISD1 TRISD0
TRISE
—
—
—
—
TRISE3
TRISE2 TRISE1 TRISE0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
Note 1: Applies to ECCP modules only.
* Page provides register information.
Register
on Page
229
208*
208*
89
90
91
92
94
95
96
199
200
195*
195*
124
127
130
133
136
 2010 Microchip Technology Inc.
Preliminary
DS41414A-page 211