PIC16F1946 Datasheet, PDF(35/440 Page) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

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PIC16F1946 Datasheet, PDF (35/440 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

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PIC16F/LF1946/47

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on all

other

Resets

Bank 2

100h(2) INDF0

101h(2) INDF1

102h(2) PCL

103h(2) STATUS

104h(2) FSR0L

105h(2) FSR0H

106h(2) FSR1L

107h(2) FSR1H

108h(2) BSR

109h(2) WREG

10Ah(1, 2) PCLATH

10Bh(2) INTCON

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

â

â

â

TO

PD

Z

DC

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

â

â

â

BSR<4:0>

Working Register

â Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

INTE

IOCIE TMR0IF INTF

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

C

IOCIF

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

10Ch

LATA

PORTA Data Latch

xxxx xxxx uuuu uuuu

10Dh

LATB

PORTB Data Latch

xxxx xxxx uuuu uuuu

10Eh

LATC

PORTC Data Latch

xxxx xxxx uuuu uuuu

10Fh

LATD

PORTD Data Latch

xxxx xxxx uuuu uuuu

110h

LATE

PORTE Data Latch

xxxx xxxx uuuu uuuu

111h

CM1CON0

C1ON C1OUT

C1OE

C1POL

â

C1SP C1HYS C1SYNC 0000 -100 0000 -100

112h

CM1CON1

C1INTP C1INTN C1PCH1 C1PCH0

â

â

C1NCH<1:0> 0000 --00 0000 --00

113h

CM2CON0

C2ON C2OUT

C2OE

C2POL

â

C2SP C2HYS C2SYNC 0000 -100 0000 -100

114h

CM2CON1

C2INTP C2INTN C2PCH1 C2PCH0

â

â

C2NCH<1:0> 0000 --00 0000 --00

115h

CMOUT

â

â

â

â

â

MC3OUT MC2OUT MC1OUT ---- -000 ---- -000

116h

BORCON

SBOREN

â

â

â

â

â

â

BORRDY 1--- ---q u--- ---u

117h

FVRCON

FVREN FVRRDY Reserved Reserved CDAFVR1 CDAFVR0

ADFVR<1:0>

0q00 0000 0q00 0000

118h

DACCON0

DACEN DACLPS DACOE

â

DACPSS<1:0>

â

DACNSS 000- 00-0 000- 00-0

119h

DACCON1

â

â

â

DACR<4:0>

---0 0000 ---0 0000

11Ah

SRCON0

SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000

11Bh

SRCON1

SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000

11Ch

â

Unimplemented

â

â

11Dh

APFCON

P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL 0000 0000 0000 0000

11Eh

CM3CON0

C3ON C3OUT

C3OE

C3POL

â

C3SP C3HYS C3SYNC 0000 -100 0000 -100

11Fh

CM3CON1

C3INTP C3INTN C3PCH1 C3PCH0

â

â

C3NCH<1:0> 0000 --00 0000 --00

Legend:

Note 1:

2:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as â0â, r = reserved.

Shaded locations are unimplemented, read as â0â.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred

to the upper byte of the program counter.

These registers can be addressed from any bank.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS41414A-page 33

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