PIC16F1946 Datasheet, PDF(33/440 Page) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

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PIC16F1946 Datasheet, PDF (33/440 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

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PIC16F/LF1946/47

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on all

other

Resets

Bank 0

000h(2) INDF0

001h(2) INDF1

002h(2) PCL

003h(2) STATUS

004h(2) FSR0L

005h(2) FSR0H

006h(2) FSR1L

007h(2) FSR1H

008h(2) BSR

009h(2) WREG

00Ah(1, 2) PCLATH

00Bh(2) INTCON

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

â

â

â

TO

PD

Z

DC

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

â

â

â

BSR<4:0>

Working Register

â Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

INTE

IOCIE TMR0IF INTF

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

C

IOCIF

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

00Ch

PORTA

PORTA Data Latch when written: PORTA pins when read

xxxx xxxx uuuu uuuu

00Dh

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

00Eh

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx uuuu uuuu

00Fh

PORTD

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx uuuu uuuu

010h

PORTE

PORTE Data Latch when written: PORTE pins when read

xxxx xxxx xxxx uuuu

011h

PIR1

TMR1GIF ADIF

RCIF

TXIF

SSPIF

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h

PIR2

OSFIF

C2IF

C1IF

EEIF

BCLIF

LCDIF

C3IF CCP2IF 0000 0000 0000 0000

013h

PIR3

â

CCP5IF CCP4IF CCP3IF TMR6IF

â

TMR4IF

â -000 0-0- -000 0-0-

014h

PIR4

â

â

RC2IF

TX2IF

â

â

BCL2IF SSP2IF --00 --00 --00 --00

015h

TMR0

Timer0 Module Register

xxxx xxxx uuuu uuuu

016h

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

017h

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

018h

T1CON

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN T1SYNC

â

TMR1ON 0000 00-0 uuuu uu-u

019h

T1GCON

TMR1GE T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS<1:0>

0000 0x00 uuuu uxuu

01Ah

TMR2

Timer 2 Module Register

0000 0000 0000 0000

01Bh

PR2

Timer 2 Period Register

1111 1111 1111 1111

01Ch

T2CON

â

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0> -000 0000 -000 0000

01Dh

â

Unimplemented

â

â

01Eh

CPSCON0

CPSON CPSRM

â

â

CPSRNG1 CPSRNG0 CPSOUT T0XCS 00-- 0000 00-- 0000

01Fh

CPSCON1

â

â

â

CPSCH<4:0>

---0 0000 ---0 0000

Legend:

Note 1:

2:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as â0â, r = reserved.

Shaded locations are unimplemented, read as â0â.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred

to the upper byte of the program counter.

These registers can be addressed from any bank.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS41414A-page 31

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