PIC16F1946 Datasheet, PDF (315/440 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16F/LF1946/47
FIGURE 24-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RXx/DTx
pin
TXx/CKx pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCxIF bit
(Interrupt)
Read
RCxREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 24-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUD1CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
300
BAUD2CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
300
INTCON
GIE
PEIE TMR0IE INTE
IOCIE TMR0IF INTF
IOCIF
89
PIE1
—
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
90
PIE4
—
—
RC2IE TX2IE
—
—
BCL2IE SSP2IE
93
PIR1
—
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
94
PIR4
—
—
RC2IF TX2IF
—
—
BCL2IF SSP2IF
93
RC1REG
EUSART1 Receive Register
294*
RC1STA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
299
RC2REG
EUSART2 Receive Register
294*
RC2STA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
299
SP1BRGL
EUSART1 Baud Rate Generator, Low Byte
301*
SP1BRGH
EUSART1 Baud Rate Generator, High Byte
301*
SP2BRGL
EUSART2 Baud Rate Generator, Low Byte
301*
SP2BRGH
EUSART2 Baud Rate Generator, High Byte
301*
TX1STA
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
298
TX2STA
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
298
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.
* Page provides register information.
 2010 Microchip Technology Inc.
Preliminary
DS41414A-page 313