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PIC16F1946 Datasheet, PDF (37/440 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology
PIC16F/LF1946/47
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 4
200h(2) INDF0
201h(2) INDF1
202h(2) PCL
203h(2) STATUS
204h(2) FSR0L
205h(2) FSR0H
206h(2) FSR1L
207h(2) FSR1H
208h(2) BSR
209h(2) WREG
20Ah(1, 2) PCLATH
20Bh(2) INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
DC
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
Working Register
— Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
20Ch
—
Unimplemented
—
—
20Dh
WPUB
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Eh
—
Unimplemented
—
—
20Fh
—
Unimplemented
—
—
210h
—
Unimplemented
—
—
211h
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
212h
SSP1ADD
ADD<7:0>
0000 0000 0000 0000
213h
SSP1MSK
MSK<7:0>
1111 1111 1111 1111
214h
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
215h
SSP1CON1 WCOL SSPOV SSPEN
CKP
SSPM<3:0>
0000 0000 0000 0000
216h
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN
RCEN
PEN
RSEN
SEN 0000 0000 0000 0000
217h
SSP1CON3 ACKTIM PCIE
SCIE
BOEN
SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
—
Unimplemented
—
—
219h
SSP2BUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
21Ah
SSP2ADD
ADD<7:0>
0000 0000 0000 0000
21Bh
SSP2MSK
MSK<7:0>
1111 1111 1111 1111
21Ch
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
21Dh
SSP2CON1 WCOL SSPOV SSPEN
CKP
SSPM<3:0>
0000 0000 0000 0000
21Eh
SSP2CON2
GCEN ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN 0000 0000 0000 0000
21Fh
SSP2CON3 ACKTIM PCIE
SCIE
BOEN
SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
 2010 Microchip Technology Inc.
Preliminary
DS41414A-page 35