PIC18F6520-I Datasheet, PDF (73/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
6.0 EXTERNAL MEMORY
INTERFACE
Note:
The External Memory Interface is not
implemented on PIC18F6X20 (64-pin)
devices.
The External Memory Interface is a feature of the
PIC18F8X20 devices that allows the controller to
access external memory devices (such as Flash,
EPROM, SRAM, etc.) as program or data memory.
The physical implementation of the interface uses 27
pins. These pins are reserved for external address/data
bus functions; they are multiplexed with I/O port pins on
four ports. Three I/O ports are multiplexed with the
address/data bus, while the fourth port is multiplexed
with the bus control signals. The I/O port functions are
enabled when the EBDIS bit in the MEMCON register
is set (see Register 6-1). A list of the multiplexed pins
and their functions is provided in Table 6-1.
As implemented in the PIC18F8X20 devices, the
interface operates in a similar manner to the external
memory interface introduced on PIC18C601/801
microcontrollers. The most notable difference is that
the interface on PIC18F8X20 devices only operates in
16-bit modes. The 8-bit mode is not supported.
For a more complete discussion of the operating modes
that use the external memory interface, refer to
Section 4.1.1 “PIC18F8X20 Program Memory
Modes”.
REGISTER 6-1:
MEMCON REGISTER
R/W-0
U-0
R/W-0
EBDIS
—
WAIT1
bit7
6.1 Program Memory Modes and the
External Memory Interface
As previously noted, PIC18F8X20 controllers are
capable of operating in any one of four program
memory modes, using combinations of on-chip and
external program memory. The functions of the multi-
plexed port pins depend on the program memory
mode selected, as well as the setting of the EBDIS bit.
In Microprocessor Mode, the external bus is always
active and the port pins have only the external bus
function.
In Microcontroller Mode, the bus is not active and
the pins have their port functions only. Writes to the
MEMCOM register are not permitted.
In Microprocessor with Boot Block or Extended
Microcontroller Mode, the external program memory
bus shares I/O port functions on the pins. When the
device is fetching or doing table read/table write
operations on the external program memory space, the
pins will have the external bus function. If the device is
fetching and accessing internal program memory loca-
tions only, the EBDIS control bit will change the pins
from external memory to I/O port functions. When
EBDIS = 0, the pins function as the external bus.
When EBDIS = 1, the pins function as I/O ports.
Note:
Maximum FOSC for the PIC18FX520 is
limited to 25 MHz when using the external
memory interface.
R/W-0
U-0
WAIT0
—
U-0
R/W-0 R/W-0
—
WM1
WM0
bit0
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
EBDIS: External Bus Disable bit
1 = External system bus disabled, all external bus drivers are mapped as I/O ports
0 = External system bus enabled and I/O ports are disabled
Unimplemented: Read as ‘0’
WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 TCY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
Unimplemented: Read as ‘0’
WM<1:0>: TBLWRT Operation with 16-bit Bus bits
1x = Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when
TABLAT<1> written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB)
will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2004 Microchip Technology Inc.
DS39609B-page 71