PIC18F6520-I Datasheet, PDF (373/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
Program Memory ............................................................... 39
Access for PIC18F8X20 Program
Memory Modes .................................................. 40
Instructions ................................................................. 45
Interrupt Vector .......................................................... 39
Map and Stack for PIC18FXX20 ................................ 40
Maps for PIC18F8X20 Program Memory Modes ....... 41
PIC18F8X20 Modes ................................................... 39
Reset Vector .............................................................. 39
Program Memory Write Timing Requirements ................. 326
Program Verification and Code Protection ....................... 253
Associated Registers ............................................... 253
Configuration Register Protection ............................ 257
Data EEPROM Code Protection .............................. 257
Memory Code Protection ......................................... 255
Programming, Device Instructions ................................... 259
PSP. See Parallel Slave Port.
Pulse Width Modulation. See PWM (CCP Module).
PUSH ............................................................................... 288
PWM (CCP Module) ........................................................ 154
Associated Registers ............................................... 155
CCPR1H:CCPR1L Registers ................................... 154
Duty Cycle ................................................................ 154
Example Frequencies/Resolutions .......................... 155
Period ....................................................................... 154
Setup for PWM Operation ........................................ 155
TMR2 to PR2 Match ........................................ 141, 154
TMR4 to PR4 Match ................................................ 147
Q
Q Clock ............................................................................ 154
R
RAM. See Data Memory.
RC Oscillator ...................................................................... 22
RCALL ............................................................................. 289
RCON Registers .............................................................. 101
RCSTA Register
SPEN Bit .................................................................. 197
Register File ....................................................................... 47
Registers
ADCON0 (A/D Control 0) ......................................... 213
ADCON1 (A/D Control 1) ......................................... 214
ADCON2 (A/D Control 2) ......................................... 215
CCPxCON (Capture/Compare/PWM Control) ......... 149
CMCON (Comparator Control) ................................ 223
CONFIG1H (Configuration 1 High) .......................... 240
CONFIG2H (Configuration 2 High) .......................... 241
CONFIG2L (Configuration 2 Low) ............................ 241
CONFIG3H (Configuration 3 High) .......................... 242
CONFIG3L (Configuration 3 Low) ............................ 242
CONFIG3L (Configuration Byte) ................................ 41
CONFIG4L (Configuration 4 Low) ............................ 243
CONFIG5H (Configuration 5 High) .......................... 245
CONFIG5L (Configuration 5 Low) ............................ 244
CONFIG6H (Configuration 6 High) .......................... 247
CONFIG6L (Configuration 6 Low) ............................ 246
CONFIG7H (Configuration 7 High) .......................... 249
CONFIG7L (Configuration 7 Low) ............................ 248
CVRCON (Comparator Voltage
Reference Control) .......................................... 229
Device ID 1 .............................................................. 249
Device ID 2 .............................................................. 249
EECON1 (Data EEPROM Control 1) ................... 63, 80
INTCON (Interrupt Control) ........................................ 89
INTCON2 (Interrupt Control 2) ................................... 90
INTCON3 (Interrupt Control 3) ................................... 91
 2004 Microchip Technology Inc.
IPR1 (Peripheral Interrupt Priority 1) ......................... 98
IPR2 (Peripheral Interrupt Priority 2) ......................... 99
IPR3 (Peripheral Interrupt Priority 3) ....................... 100
LVDCON (Low-Voltage Detect Control) .................. 235
MEMCON (Memory Control) ..................................... 71
OSCCON ................................................................... 25
PIE1 (Peripheral Interrupt Enable 1) ......................... 95
PIE2 (Peripheral Interrupt Enable 2) ......................... 96
PIE3 (Peripheral Interrupt Enable 3) ......................... 97
PIR1 (Peripheral Interrupt Request 1) ....................... 92
PIR2 (Peripheral Interrupt Request 2) ....................... 93
PIR3 (Peripheral Interrupt Request 3) ....................... 94
PSPCON (Parallel Slave Port Control)
Register ........................................................... 129
RCON ........................................................................ 31
RCON (Reset Control) ....................................... 60, 101
RCSTAx (Receive Status and Control) ................... 199
SSPCON2 (MSSP Control 2, I²C Mode) ................. 169
SSPSTAT (MSSP Status, I²C Mode) ...................... 167
SSPSTAT (MSSP Status, SPI Mode) ...................... 158
Status ........................................................................ 59
STKPTR (Stack Pointer) ............................................ 43
Summary ............................................................. 52–55
T1CON (Timer 1 Control) ........................................ 135
T3CON (Timer3 Control) ......................................... 143
TXSTAx (Transmit Status and Control) ................... 198
WDTCON (Watchdog Timer Control) ...................... 250
Reset ................................................................. 29, 239, 289
Brown-out Reset (BOR) ........................................... 239
MCLR Reset .............................................................. 29
MCLR Reset during Sleep ......................................... 29
Oscillator Start-up Timer (OST) ............................... 239
Power-on Reset (POR) ...................................... 29, 239
Power-up Timer (PWRT) ......................................... 239
Programmable Brown-out Reset (PBOR) .................. 29
Reset Instruction ........................................................ 29
Stack Full Reset ........................................................ 29
Stack Underflow Reset .............................................. 29
Watchdog Timer (WDT) Reset .................................. 29
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements .......................................................... 327
RETFIE ............................................................................ 290
RETLW ............................................................................ 290
RETURN .......................................................................... 291
Return Address Stack
and Associated Registers .......................................... 43
Revision History ............................................................... 361
RLCF ............................................................................... 291
RLNCF ............................................................................. 292
RRCF ............................................................................... 292
RRNCF ............................................................................ 293
S
SCI. See USART.
SCK ................................................................................. 157
SDI ................................................................................... 157
SDO ................................................................................. 157
Serial Clock, SCK ............................................................ 157
Serial Communication Interface. See USART.
Serial Data In, SDI ........................................................... 157
Serial Data Out, SDO ...................................................... 157
Serial Peripheral Interface. See SPI.
SETF ............................................................................... 293
Slave Select, SS .............................................................. 157
SLEEP ............................................................................. 294
Sleep ....................................................................... 239, 252
DS39609B-page 371