PIC18F6520-I Datasheet, PDF (343/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-26: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
PIC18FXX20
PIC18LFXX20
1.6
20⁽⁵⁾
µs TOSC based, VREF ≥ 3.0V
3.0
20⁽⁵⁾
µs TOSC based, VREF full range
PIC18FXX20
2.0
6.0
µs A/D RC mode
PIC18LFXX20
3.0
9.0
µs A/D RC mode
131 TCNV Conversion Time
11
(not including acquisition time) (Note 1)
12
TAD
132 TACQ Acquisition Time (Note 3)
15
—
µs -40°C ≤ Temp ≤ +125°C
10
—
µs 0°C ≤ Temp ≤ +125°C
135 TSWC Switching Time from Convert → Sample
— (Note 4)
136 TAMP Amplifier Settling Time (Note 2)
1
—
µs This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1:
2:
3:
4:
5:
ADRES register may be read on the following TCY cycle.
See Section 19.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when
input voltage has changed more than 1 LSb.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels
is 50Ω.
On the next Q4 cycle of the device clock.
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
 2004 Microchip Technology Inc.
DS39609B-page 341