PIC18F6520-I Datasheet, PDF (13/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
PIC18F6X20 PIC18F8X20 ^Type
Buffer
Type
Description
MCLR/VPP
MCLR
VPP
7
9
Master Clear (input) or programming
voltage (output).
I
ST
Master Clear (Reset) input. This pin is
an active-low Reset to the device.
P
Programming voltage input.
OSC1/CLKI
OSC1
CLKI
39
49
Oscillator crystal or external clock input.
I CMOS/ST Oscillator crystal input or external clock
source input. ST buffer when configured
in RC mode; otherwise CMOS.
I
CMOS
External clock source input. Always
associated with pin function OSC1
(see OSC1/CLKI, OSC2/CLKO pins).
OSC2/CLKO/RA6
40
OSC2
CLKO
RA6
50
Oscillator crystal or clock output.
O
—
Oscillator crystal output.
Connects to crystal or resonator in
Crystal Oscillator mode.
O
—
In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
I/O
TTL
General purpose I/O pin.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
 2004 Microchip Technology Inc.
DS39609B-page 11